PG Diploma in VLSI Design

Introduction to VLSI
Overview of Digital Logic Design
Verilog HDL Design Techniques
Lab Practice on Verilog
Simple Project Implementation

• Duration: 6 Weeks

• Introduction to VLSI
• Details of Digital Logic Design
• Verilog HDL Full Design Techniques
• FPGA Full Design Techniques
• Lab Practice on Verilog
• Implementation on FPGA’s
• Real Time Project Implementation

• Duration: 8 Weeks

• Introduction to VLSI
• Details of Digital Logic Design
• Verilog HDL Full Design Techniques
• FPGA Full Design Techniques
• Lab Practice on Verilog
• Implementation on FPGA’s
• Static Timing Analysis Details & Real Time Issues
• Real Time Project Implementation

• Duration: 12 Weeks

• Introduction to VLSI
• Details of Digital Logic Design
• Details of SoC Design Techniques
• Verilog HDL Full Design Techniques
• FPGA Full Design Techniques
• Lab Practice on Verilog
• Implementation on FPGA’s
• Implementation on SoC Based Tools
• Concepts of CDC
• Static Timing Analysis Details & Real Time Issues
• Real Time Project Implementation

• Duration: 12 Weeks

• Introduction & Basic Programming Concept
• Verilog Modeling Style
• Register, Net
• Datatypes, Arrays, Vectors
• Operators
• Continuous Assignment
• Procedural Assignment
• Vector Operation
• Conditional Expression, always, if, case
• Loop Statement (while, for, foreach, do-while)
• Task, Function
• Generate Block
• Parameter, Macros
• Systemtask
• Module Instantiation
• Combinational Logic Modeling
• Sequential Logic Modeling
• FSM Modeling
• Memory Modeling
• Clock Modeling, Clock Divider
• Timer
• Verilog File Handling
• TB Architecture
• Verification Environment Coding
• Testcase Bring-up
• Simulation Run
• Waveform Generation and Analysis
• Log File Analysis
• Simulation Time Data Passing
• Parameter Override from TB
• Randomization in Verilog
• Seed Passing
• Industrial Project Coding

• Duration: 10 Weeks

• TB Architecture
• Data Types, Array, Literals
• Operators
• Randomization, Constraint
• Class, OOPS
• Procedural Statements, Flow Controls (fork-join, fork-join_any, fork-join_none, wait-fork, disable-fork)
• Subroutines
• Struct, Union
• Systemtasks
• Interface, Modport, Clocking Block
• Event Scheduling
• Program Block
• Threads
• Interprocess Communication
• Virtual Interface
• Event Handling
• File Handling
• DPI
• Code Coverage and Functional Coverage
• Assertions
• TB Component Coding
• TB, TC Coding
• Stimulus Generation and Drive
• Simulation Run, Test Termination
• Error Debugging
• Log File and Waveform Analysis
• Industrial Project Coding

• Duration: 12 Weeks

• TB Architecture
• TLM (Transaction Level Modeling)
• Sequences and Items
• Sequencer, Driver, Monitor
• Env, Agent, Cov, Scoreboard, Test
• Built-in Methods
• UVM Configuration, Config DB
• Factory Override
• Callback
• UVM Event
• RAL (Register Abstraction Layer)
• Project: AXI

We are providing industrial protocol training for corporates,Institutes & Individuals.
Industrial protocol training such as:
USB,PCIe,AMBA BUS…etc

Industry standard projects in Verilog,SV,UVM

LINUX Commands

Shell Script
Perl Script
Python Script